The present invention relates to a process for preparation of a semiconductor device including forming a modified ONO structure. The modified ONO structure comprises a high-K dielectric material.
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. One EEPROM device that utilizes the ONO structure is a silicon-oxide-nitride-oxide-silicon (SONOS) type cell. A second EEPROM device that utilizes the ONO structure is a floating gate flash memory device, in which the ONO structure is formed over the floating gate, typically a polysilicon floating gate.
In SONOS devices, during programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of the electrons gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the silicon nitride layer near the source region. Because silicon nitride is not electrically conductive, the charge introduced into the silicon nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous silicon nitride layer.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory circuits that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM, which is available under the trademark MIRRORBIT(trademark) from Advanced Micro Devices, Inc., Sunnyvale, Calif. The MIRRORBIT(trademark) two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
As device dimensions continue to be reduced, the electrical thickness of the ONO layer must be reduced accordingly. Previously, this has been accomplished by scaling down the thickness of the ONO layer. However, as the ONO layer is made physically thinner, leakage currents through the ONO layer may increase, and the charge trapping ability of the nitride layer may be reduced, which limits the scaling down of the total physical thickness of the ONO layer.
A floating gate flash device includes a floating gate electrode upon which electrical charge is stored. The floating gate electrode is formed on a tunnel oxide layer which overlies a channel region residing between the source and drain regions in a semiconductor substrate. The floating gate electrode together with the source and drain regions form an enhancement transistor. Typically, the floating gate electrode may be formed of polysilicon.
In a floating gate flash device, electrons are transferred to a floating gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating gate electrode by an overlying control gate electrode. The control gate electrode is capacitively coupled to the floating gate electrode, such that a voltage applied on the control gate electrode is coupled to the floating gate electrode. The floating gate flash device is programmed by applying a high positive voltage to the control gate electrode, and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating gate electrode.
The control gate electrode is separated from the floating gate electrode by an interpoly dielectric layer, typically an oxide-nitride-oxide stack, i.e., an ONO structure or layer. However, as device dimensions continue to be reduced, the electrical thickness of the interpoly dielectric layer between the control gate electrode and the floating gate electrode must be reduced accordingly. Previously, this has been accomplished by scaling down the physical thickness of the ONO layer. However, as the ONO layer is made physically thinner, leakage current through the ONO layer may increase, which limits the scaling down of the total physical thickness of the ONO layer.
Some of the improvements in devices can be addressed through development of materials and processes for fabricating the ONO layer. Recently, development efforts have focused on novel processes and materials for use in fabrication of the ONO layer. While the recent advances in EEPROM technology have enabled memory designers to double the memory capacity of EEPROM arrays using two-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, the ONO layer must be carefully fabricated to avoid an increase in the leakage current. Accordingly, advances in ONO fabrication technology are needed to insure proper charge isolation in ONO structures used in MIRRORBIT(trademark) two-bit EEPROM devices and in floating gate flash devices.
In one embodiment, the present invention relates to a semiconductor device including a modified ONO structure, in which the modified ONO structure includes a bottom oxide layer, a layer including a composite dielectric material on the bottom oxide layer, in which the composite dielectric material includes elements of at least one high-K dielectric material, and a top oxide layer on the layer including a high-K dielectric material.
In one embodiment, the present invention relates to a non-volatile memory cell including a) a substrate including a source region, a drain region, and a channel region positioned therebetween; b) a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric film; and c) a control gate positioned above the floating gate and separated from the floating gate by an interpoly dielectric layer, the interpoly dielectric layer including a bottom silicon dioxide layer adjacent to the floating gate, a top silicon dioxide layer adjacent to the control gate, and a center layer including a high-K dielectric material and positioned between the bottom silicon dioxide layer and the top silicon dioxide layer.
In another embodiment, the present invention relates to a non-volatile memory cell including a) a substrate including a source region, a drain region, and a channel region positioned therebetween; b) a charge storage layer including a modified ONO structure, having a bottom silicon dioxide layer adjacent the channel region, a top silicon dioxide layer, and a center charge storage layer including a high-K dielectric material layer and positioned between the bottom silicon oxide layer and the top silicon dioxide layer; and c) a gate capacitively coupled to the channel region through the charge storage layer.
In one embodiment, the present invention relates to a process for fabrication of a semiconductor device including a non-volatile memory cell having a modified ONO structure, including forming the modified ONO structure by steps comprising providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a high-K dielectric material layer on the first oxide layer; and forming a top oxide layer on the high-K dielectric material layer.
In another embodiment, the present invention relates to a process for fabrication of a two-bit EEPROM device including a modified ONO structure, including forming the modified ONO structure by steps including providing a semiconductor substrate; forming a first or tunnel oxide layer overlying the semiconductor substrate; depositing a high-K dielectric material layer overlying the tunnel oxide layer; and forming a top oxide layer overlying the high-K dielectric material layer.
In yet another embodiment, the present invention relates to a process for fabrication of a floating gate flash device including a modified ONO structure, including forming the modified ONO structure by steps comprising providing a semiconductor substrate having a floating gate electrode; forming a first or bottom oxide layer overlying the floating gate electrode; depositing a high-K dielectric material layer overlying the bottom oxide layer; and forming a top oxide layer overlying the high-K dielectric material layer.
In one embodiment, the present invention relates to a non-volatile memory cell including a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric film; and c) a control gate positioned above the floating gate and separated from the floating gate by an interpoly dielectric layer, the interpoly dielectric layer comprising a single layer adjacent to both the floating gate and the control gate, the single layer comprising a dielectric material, wherein the dielectric material is a metal silicate, a metal aluminate or a metal mixed-aluminate/silicate.
Thus, in the present invention, by use of a high-K dielectric material which replaces the nitride layer fully or partially, a modified ONO-type structure may be fabricated having reduced dimensions without degrading leakage current and electrical properties of the modified ONO structure and without sacrificing the charge trapping ability of the modified ONO structure in the two-bit EEPROM device. For the modified ONO structure in flash memory devices, the present invention provides advantages such as (1) reduction of equivalent oxide thickness of next generation devices; (2) composite high-K layers may provide improved charge trapping compared to nitride; (3) devices with high-K films for ONO structures are expected to have improved data retention and reliability; and (4) the high-K dielectric material layer allows fabrication of a modified ONO layer which is physically thicker, resulting in fewer charge leakage paths within the modified ONO structure. A variety of high-K dielectric materials may be used for a fall or partial replacement of the nitride layer of an ONO structure, to obtain a modified ONO structure. The high-K dielectric materials may be formed in a nano-laminate structure, allowing for exact selection of composition, thickness and K value of the modified ONO structure. Thus, the present invention provides an advance in ONO fabrication technology, and ensures proper charge isolation in modified ONO structures used in MIRRORBIT(trademark) two-bit EEPROM devices, ensures proper dielectric separation of the control gate electrode from the floating gate electrode in a floating gate flash device, and helps in scaling down the electrical thickness of ONO structures for next generation flash memory devices, while at the same time providing distinct process and economic advantages.
Although described herein in terms of MIRRORBIT(trademark) two-bit EEPROM devices and floating gate flash devices, the present invention is broadly applicable to fabrication of any semiconductor device that includes an ONO structure.